Currently, eFUSE (electric fuse) type elements which are described in the following Patent Documents 1 and 2 and Non-patent Document 1 have been known as a memory element that can be utilized as a ROM (Read Only Memory).
Each of the eFUSE type memory elements described in Patent Document 1 and Non-patent Document 1 includes memory cells connected in series to a selection transistor. At a writing operation time, the selection transistor is set to a conducting state in a selected memory cell, a large current is flown to the memory element, and a current/voltage characteristic of the memory element is changed from a resistance characteristic of low resistance to an insulation state by fusing the memory element, and writing of binary data is performed.
In the memory cells described in Patent Document 1, a terminal, which is not connected to the selection transistor, of the memory element is connected in common to a first voltage supply line. A terminal, which is not connected to the memory element, of the selection transistor is connected in common to a second voltage supply line. A second transistor that is brought into a conducting state at a writing operation time of the memory element is connected to a second voltage supply line so that a writing circuit is formed. There is formed a writing current path that passes from the first voltage supply line via the memory cell as a target of writing and the second transistor. A large current flows in the memory element so that writing of the memory element is executed.
In the memory cells described in Non-patent Document 1, a terminal which is not connected to the selection transistor, of the memory element is connected in common to a bit line. A terminal, which is not connected to the memory element, of the selection transistor is grounded. A second transistor that is brought into a conducting state at a writing operation time of the memory element is connected to the bit line so that a writing circuit is formed. There is formed a writing current path that passes from the second transistor via the bit line and the memory cell as a target of writing. A large current flows in the memory element so that writing of the memory element is executed.
The memory element described in Patent Document 2 is configured as a resistance element including a lamination structure of polysilicon/silicide/silicon nitride films that is the same as a wiring structure employed in a normal logic LSI process with two terminals of a cathode and an anode. A large current flows in the resistance element for heating, an atom of a material for a metal wire is migrated or melted in a direction of an electron flow to cause breakdown, and then a resistance value between two terminals is changed. In Patent Document 2, an example of configuring the memory element as a memory cell is not disclosed. However, two MOS transistors are connected in series to the memory element, and a large current is configured to be flown at the writing time via the MOS transistor.